The present invention relates generally to a method of attaching semiconductor die to lead frame, and more particularly to a flip-chip on lead frame method of attaching semiconductor die to the lead frame.
Demand of product complexity keep increasing in an astounding rate and there is a pressing need in the industry to increase the semiconductor die size in order to add in more functionality to provide such complex products. Yet, at the same time there is also more pressing need in the industry to reduce the overall package size, especially due to miniaturization. In the past, this pressing issue has been somewhat satisfactorily resolved by utilizing the Ball Grid Array method (BGA) as a packaging solution to solve such problem. However, such BGA""s method is not a cost-effective solution for assembling the low pin count lead frame-based product such as the Shrink Small Outline Package (SSOP), Small Outline Transistor (SOT) or the likes. This is mainly due to the high substrate cost in comparison to the standard lead frame cost. Consequently, many product designers have not seen transition from the generally known practice to the flip-chip technology, especially for the low pin count devices, as an economically viable option.
The process flow for flip-chip on BGA method generally involves flipping a bumped die onto a BGA substrate (normally organic or ceramic nature), underfilling, molding, ball attachment and singulation. As mentioned earlier, the relative cost of the substrate to lead frame is higher, therefore the transition of using such technique to produce low pin count devices is not particularly acceptable or popular.
Nevertheless, there is disclosed a method of fabricating flip-chip on leads devices, as in U.S. Pat. No. 5,817,540, to assembled low pin count semiconductor devices. Generally, such method is said to have provided a large and robust flip-chip type interconnections between the electric contact points and the lead frame, eliminating the need for wirebonding and for adhesive connections of the lead frame to the die active surface. The disclosed method generally comprises of the concept of flipping a die onto a lead frame with the use of bumps as interconnect. Wafer will be bumped and saw beforehand. Bumping method will be as per what is used for the current flip-chip technology. Upon separating the dies, the bumped die will be flipped directly onto the matching lead frame. Connection between the die and the lead frame is achieved through re-flowing of the solder. When solder bumps are not used as an interconnection, conductive paste or conductive-filled epoxy may also be used. In such a case, conductive paste will be deposited onto the die by silk screening or any other method known in the art. Connection will then be achieved through the curing of paste in an oven or in-line furnace, as generally known in the art. Die placement accuracy needed for this invention is xc2x12 mils (5.08 micrometers). After the die-to-lead frame assembly, a dielectric layer, or the under-fill material, will be dispensed to cover the gap existed between the die and the lead frame, primarily for preventing potential shorting and to further promote adhesion between the die and the lead frame. Final encapsulation is accomplished using the conventional overmold process known in the art. This method, in particular, is suitable to assemble DRAM devices.
Although the disclosed U.S. Pat. No. 5,817,540 method do offer certain advantages, it also permit potential shorting to develop between the adjacent solder bumps or lead fingers. In particular, this is due to the direct re-flow of the solder bumps onto the lead frame that causes the solder to collapse completely onto the lead frame thus giving very little or no gap between the die and the lead frame. Consequently, shorting may develop between adjacent bumps or the lead fingers in addition to the uneven under-fill or mold compound coverage. Furthermore, the difficulty to ensure consistent gap between the die and lead frame is also prevalent using this method.
The present invention seeks to provide an alternative solution to the known flip-chip on lead frame method of assembling semiconductor devices. The proposed invention generally offer one step encapsulation process to promote adhesion of die to the lead finger and prevent the potential of shorts from developing between the adjacent bumps or lead fingers. Such advantageous features may be achieved through the use of conventional mold equipment and mold compound. Generally, mold compound is used for the same purpose as under-fill in any of the flip-chip construction to reduce localized stress caused by coefficient of thermal expansion (CTE) mismatch between the die and substrate, or the lead frame. This is particularly important in promoting greater mechanical robustness of the semiconductor devices. With one encapsulation step proposed by the present invention, manufacturing process is made simpler, faster and relatively cheaper.
It is therefore an object of the present invention to provide a method of attaching a semiconductor die to a lead frame suitable for producing low pin count semiconductor devices.
It is another object of the present invention to provide a flip-chip-type method of attaching semiconductor die to a lead frame.
Yet, it is another object of the present invention to provide a single encapsulation step of packaging semiconductor devices, yet offering a substantially reduced localized stress causes by the coefficient thermal expansion mismatch.
Yet, it is another object of the present invention to provide a method of attaching semiconductor die to lead frame that is able to accommodates larger die size in a comparatively smaller packaging dimension.
These and other objects of the present invention are accomplished by providing,
A flip-chip-type method of attaching a semiconductor die (11) to a lead frame (12), comprising the steps of:
configuring said semiconductor die (11) with a plurality of predetermined electric contact points (10) so as to accommodate connection to lead fingers of said lead frame (12);
configuring discrete conductive element (13) over each of said predetermined electric contact points (10);
depositing a solder element to form solder element layers (14) on said lead fingers, said solder element layers (14) are arranged at locations that match with said discrete conductive elements (13); and
securing said semiconductor die (11) to said lead frame (12) through said electric contact points (10), said discrete conductive elements (13) and said solder element layers (14), respectively.
Preferably, the semiconductor device is encapsulated using mold compound in a single encapsulation process.
Also preferable, the method may also be adapted to assemble higher pin count semiconductor devices.
Also preferable, the solder element layers are set to melt at substantially lower temperature compared to the discrete conductive elements.
Yet, the solder element is deposited onto the lead finger through stencil printing or any other suitable methods.
Yet, it is also preferable that the solder element is deposited onto the lead fingers through selective plating.